Memory management unit and method of accessing an address

ABSTRACT

A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

FIELD OF THE INVENTION

The present invention relates to a memory management unit and method ofaccessing an address in physical address space. The invention isapplicable to, but not limited to, extending address space using amemory management unit.

BACKGROUND OF THE INVENTION

In the field of 8-bit and 16-bit microcontroller control units (MCUs),there is an increasing trend towards integrating ever-larger memoryelements onto the MCUs, and accessing the data elements/individualaddresses in these larger memory elements. For example, there is aconsumer-driven demand to provide 128 Kbyte memory, and potentially 256Kbytes (and more), of memory on an 8/16-bit MCU.

8/16-bit MCUs typically have a program counter that comprises 16-bitsand instructions with addressing modes that only cater for up to a16-bit address. This results in an addressable limit of 65,536 locations(i.e. the number of combinations of 16 0's and 1's). Thus, it is knownthat the program counter associated with MCUs is the limiting factor inaccessing physical address space and consequently many current 8/16-bitMCUs are limited in that they are unable to support addressing anassociated memory above 64 Kbytes.

Within MCUS, it is also known that a number of memory management units(MMUs) exist that comprise paging access mechanisms to access pagedmemory. However, it is also known that these paging access mechanismsfail to support accessing a particular memory line for data access in anefficient and easily usable manner.

Paged memory (sometimes referred to as banked memory) is a term that isused to describe a remapping of physical memory to an address within theaddress capability of the MCU device. An example of code required toaccess data in such a paged memory would typically be of the formillustrated in FIG. 1.

A page is typically a specific size, which is less than the addressablememory range of the device but is less than the physical address spacedesired. When accessing physical memory through this ‘page’ it may benecessary to re-map another page into the page's area, if the nextsequential byte required is not within the current page. In addition,the index pointing to the paged memory typically needs to be adjusted topoint to the start of the paged memory. Access to memory is non-linearand non-contiguous.

In typical paged memory designs there are two major issues in accessingpaged memory for data, where both issues are known to severely impactperformance:

-   -   (i) If code is executing from paged memory it is necessary to        call a routine in unpaged memory to access data in another page,        and make this available to the calling code.    -   (ii) As is often the case, data cannot fit within a single page        and, thus, spans multiple pages. As a consequence, access        mechanisms are very limited to accessing a particular page, for        example accessing only 4K of memory, or a significant amount of        effort is expended in order to access (for example check and        update the page and pointer) data within the page space that        crosses multiple pages.

Thus, a need exists for a microprocessor memory management unit andmechanism therefor that enables data in memory space to be accessed in amore efficient manner.

SUMMARY OF THE INVENTION

In accordance with aspects of the present invention, there is provided amemory management unit (MMU) and method of operation therefor, asdefined in the appended Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of code required to access data in a knownpaged access mechanism.

Exemplary embodiments of the present invention will now be described, byway of example only, with reference to the accompanying drawings, inwhich:

FIG. 2 illustrates an 8/16-bit micro-controller architecture accordingto one embodiment of the present invention;

FIG. 3 illustrates a linear memory management unit according to oneembodiment of the present invention; and

FIG. 4 illustrates a method of operation of a linear memory managementunit (LMMU) according to one embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

One embodiment of the present invention will be described in terms of an8/16-bit microprocessor control unit that supports a method ofaddressing, say, 128 Kbytes of memory using, say, a linear memorymanagement unit (LMMU) that operates on this extended address range incombination with the MCU normal addressing capability of say 64K.

Notably, an L register is provided that is arranged to be a greateraddressable size than the program counter in prior art arrangements.Notably, when the L register is placed on the address bus it isconfigured such that it is able to exceed the limits of the programcounter. Thus, in this manner, the ‘L’ register effectively becomes theprogram counter for data access read/write operations. In effect, theaddress space that was provided by the program counter in prior artarrangements has been extended by the ‘L’ register.

In one embodiment of the present invention, an automatic incrementing ofthe address accessed using the ‘L’ register is facilitated, therebyalleviating or negating the need to check the accessing of memory.

The inventive concept is applicable to, but not limited to, extendingdata address space with a memory management unit in a micro-controllerunit (MCU). Advantageously, the extended data address space provides acontiguous data space and is achieved in an easy to use manner. Thecontiguous data space is achieved by providing a pointer that is ableaccess data space by starting at, say, a bottom of the address space andextend to, say the top of the address space. Furthermore, the inventiveconcept supports byte and multi-byte access with an optionalauto-incrementing pointer as well as supporting pointer arithmetic.

In the context of the present invention, ‘linear address space’encompasses the concept of a pointer that can be positioned at abeginning of an address space of the ‘L’ register and being able to bepointed to the end of the ‘L’ register without the need to loop values.In this regard each successive address increments. Hence, in the contextof the present invention, the term ‘linear’, when referenced toaccessing memory, encompasses an ability to access memory contiguously.This is in contrast to the known paging mechanisms that continuouslyloop, i.e. successively loop around ‘0-9’ values.

In this regard, it is possible to access substantially all of a completephysical memory address space. In the context of the present invention,the definition of ‘physical memory address space’ encompasses how muchreal memory (address space) the MCU contains. The physical memoryaddress space is larger than the addressable space of the MCU device,which is limited by the program counter's capabilities. The addressablespace of the MCU encompasses how much the core processor is able to readfrom or write to memory unsupported. Thus, as substantially all of acomplete physical memory address space is now accessible (for example byarranging the ‘L’ register to comprise 3 bytes (=24 bits) equating to a16 Mbit address range that is significantly greater than the 64 kbitaddress space of a known program counter), there is no need to check forboundary conditions. Thus, the inventive concept extends the dataaddress space to the limit of the L register and therefore beyond thelimit imposed by the program counter.

For example, one set of code that supports the aforementioned linearaccess mechanism may be of the form:

  ; L - pointer to start of data   ; loopcount - size of data Loop:  LDA [L+]   Code to process data . . .   DEC loopcount   BNE loop.

Notably, data space in embodiments of the present invention is organisedwith its physical address being accessible through a linear memorymanagement unit (LMMU). The inventive concept of the present inventionallows simple access to a linear address space for data through amemory-mapped indirect register with an auto adder capability. Notably,this access to a linear address space for data is achieved withoutrequiring any modifications to the instruction set or core.

Referring now to FIG. 2, a microprocessor architecture 200 according toone embodiment of the present invention is illustrated. Themicroprocessor architecture 200 comprises an 8/16-bit core (centralprocessing unit (CPU)) 205 operably coupled to physical address space260 via a data communication bus 210.

The CPU 205 is also operably coupled to a linear memory management unit(LMMU) 220 via address communication bus 215. The LMMU 220, in oneembodiment of the present invention, is arranged as a pointer LMMU. Inthis embodiment, the pointer linear management memory unit (LMMU) 220provides access to a linear, non-segmented contiguous data space that islarger than the native address capability of the underlying processorarchitecture.

In one embodiment of the present invention, it is envisaged that the ‘L’register may be divided into multiple elements, such as registers L2,L1, L0, to provide more ways of accessing L via the processor (say, the8/16-bit core). In one embodiment of the present invention, the numberof bits in the ‘L’ pointer determines the addressable range of the LMMU220. For example, with a register ‘L’ of 24 bits, an addressable rangeof 2̂⁽²⁴⁾ for the LMMU 220 may be achieved, i.e. 16 Mbytes would beaccessible. Alternatively, with a register ‘L’ of 32 bits, anaddressable range of 2̂⁽³²⁾ for the LMMU 220 may be achieved, i.e. 4Gbytes would be accessible.

The linear management memory unit (LMMU) 220 also provides a linearaddressing mode for all instructions that are capable of addressing theLMMU via an extended address bus 235, as will be described later withrespect to FIG. 3. The way in which the LMMU 220 is designed enhancesthe addressing modes of the processor by effectively adding extendedaddressing to all instructions that can access the [L] register.

The LMMU 220 comprises register and control logic 225, that isaccessible by the CPU 205 via both the data communication bus 210 andthe address communication bus 215, as further described with respect toFIG. 3. The register and control logic 225 comprises a register decoder(not shown) for decoding register addresses transmitted on the datacommunication bus 210.

The LMMU 220 further comprises an output multiplexer 230 that isoperably coupled to register and control logic 225 as well as the CPU205 via the address communication bus 215. The output multiplexer 230 isoperably coupled to the physical address space 270 of the physicaladdress space 260 via the extended address bus 235 supported by thememory management unit 200 of the present invention.

Referring now to FIG. 3, the linear memory management unit 220 accordingto one embodiment of the present invention is further illustrated. TheLMMU 220 comprises register and control logic 225 having an output 315coupled to output multiplexer 230. The output multiplexer 230 provides amultiplexed output on an extended address bus 235. The address placedupon the extended address bus is either the program counter or thecontents of the L register. The L register being placed on the extendedaddress bus whenever access to registers [L] or [L+] is made, otherwisethe extended address bus will be set to the value of the program counterwith high order extended address bits not provided by the programcounter set to ‘0’.

A control line 360 is also connected from the register and control logic225 to the output multiplexer 230 to arrange data placed on the extendedaddress bus 235.

The register and control logic 225 also provides an output 370 tomultiplexer logic 310. The multiplexer 310 comprises a control input 365from the register and control logic 225. The multiplexer 310 alsocomprises a logical ‘1’ input. The provision of a logical ‘1’ input, sayto one or more logic gates (not shown) in the multiplexer enables thevalue from the AIL register to be passed to an arithmetic logic unit305, or an adder to the L register of either [L+], [L], etc., whichadditionally receives a feedback signal 315 from the output of theregister and control logic 225.

In accordance with one embodiment of the present invention, the registerand control logic 225 is arranged to provide a pointer utilisingarithmetic logic unit 305 to provide ‘L’ index manipulation. Registerand control logic 225 comprises a number of registers, as detailed belowin Table 1.

TABLE 1 Name Use L L′ index register [L+] Accesses data pointed to bycontents of ‘L’ index register, each access increments L by one [L]Accesses data pointed to by contents ‘L’ index register AIL ADD to Lindex register

Thus, the ‘L’ index manipulation, that is accessing data in register andcontrol logic 225 may be performed using:

-   -   (i) incrementing the pointer 375 using (L+) value 345;    -   (ii) adding a value to the pointer 375 using the AIL value 355.        It is envisaged that the adding function using the AIL value 355        may include XOR logic in addition to, or as an alternative to,        an adder logic; or    -   (iii) performing no movement of the pointer 375 (i.e. the        pointer stays directed to the same position on the [L] register        350. In this manner, the value in the [L] register 350 is placed        on the address bus, but the ‘L’ register is not incremented.

Thus, an ‘L’ register resides in a memory map of a normal register. Whenread/write operations to the L+register are performed, as pointed to bythe L register, these operations are often termed ‘indirect addressingoperations’ as they are looking at a place where the L register ispointing to.

Thus, an ‘auto adder’ function us supported that performs read/writeoperations by use of the L+ value to automatically add ‘1’ to thepointer value. The provision of such an ‘auto adder’ function wouldnormally require modification to the instruction set or core. However,and advantageously, if, say, a 24-bit address is required, the inventiveconcept supports instructions having a 24-bit address without the needto modify the core to support a 24-bit program counter.

In one embodiment of the present invention, it is envisaged that thearithmetic logic unit may be replaced with any suitable arithmetic logicunit, which may in some instances be an adder or a subtractor.

In one embodiment of the present invention, a size of the ‘L’ pointer(e.g. the size of the ‘L’ register used to address a size of physicalmemory wished to be accessed) is arranged to be flexible so that thepointer can be easily directed to any address of the physical memory.The size of the L register is determined by the size of theextended/physical address space being implemented during the design ofthe MCU. For example an 18-bit L register would allow the addressing of131072 locations, whereas a 24-bit L register would allow the addressingof 16.8 Mbytes.

Thus, the LMMU 220 incorporates an arithmetic logic unit (ALU) such asarithmetic logic unit 305, which allows a value to be added to the ‘L’pointer. By accessing register [L] the address bus can be set to thevalue of the L register and read/write operations of the CPU 205reference this address in memory.

Following access to the pointer ‘L’ 340, via the index register ‘L+’345, the pointer to the ‘L’ register will increment be incremented by‘1’.

In one embodiment of the present invention, it is envisaged that bymapping the [L+] register 345 to more than one memory location it ispossible for the LMMU 220 to perform multi-byte memory accesses whilstcorrectly incrementing the ‘L’ register. Thus, a multi-byte read/writeoperation may be employed.

For example, an 8-bit MCU 205 may be configured to support 16-bitread/write operations as multiple 8-bit transfers. By utilising the [L+]register 345 in multiple adjacent locations, the [L] register 320 willbe incremented after the first read/write operation and subsequently byeach of the remaining 8-bit transfers. Such an embodiment advantageouslysupports sequential access to multiple bytes of a larger word size. Forexample four bytes of a larger word size may be facilitated by definingfour sequential instances of L+ 345. After each access to the L+register 345 the ‘L’ register will have been updated by four.

In one embodiment of the present invention, it is envisaged that writinga 2's compliment (−128 to +127) to register AIL 355 will cause the AILregister value to be added (for positive values) or subtracted (fornegative values) to the [L] register 350.

Referring now to FIG. 4, a method 400 of operation of a linear memorymanagement unit (LMMU) is illustrated according to one embodiment of thepresent invention. The method commences in step 405 with an MCU(processing core) wishing to access or write to physical address space.The MCU accesses or writes to the physical address space using a linearmanagement function that comprises register and control logic.

The register and control logic comprises a number of mechanisms forwriting values to or reading values from the physical address space. Afirst mechanism, shown in step 410 is reading the memory mapped registerL that retrieves the contents of the L pointer. Accessing the [L] memorymapped register places the contents of the ‘L’ pointer onto the addressbus and thus the associated read/write operation is re-directed to thephysical memory location defined by the contents of the L register.

A second mechanism is writing a value to the memory mapped register L,which sets the L pointer to the value that has been written, as shown instep 415. Writing a value to the memory mapped register [L] sets the ‘L’pointer to the value written.

A third mechanism comprises writing a value to the memory mappedregister [AIL], as shown in step 420. This operation has the effect ofadding the value to the ‘L’ pointer. Additional registers can be sodefined to enable other operations of the ALU to be performed.

A fourth mechanism comprises writing a value to, or reading a value fromthe memory mapped register [L+], as shown in step 425. Accessing the[L+] memory mapped register places the contents of the L pointer ontothe extended address bus, in step 430. Thus, the associated read/writeoperation is re-directed to the physical memory location defined by thecontents of the L register, as shown in step 435. After accessing the[L+] register the L register is incremented by ‘1’, as indicated in step440.

It will be understood that the aforementioned flexible registeraddressing arrangement of the memory management unit (MMU), and methodof operation therefor, aims to provide at least one or more of thefollowing advantages:

-   -   (i) The inventive concept provides improved access to data from        code running in paged memory.    -   (ii) The inventive concept provides easier access to large        linear data elements without a need to detect page changes.    -   (iii) There is no need to conditionally reset a pointer to point        to a paging window, as required in known paged methods.    -   (iv) The inventive concept provides auto incrementing of a        register ‘L’ pointer, reducing overhead associated with        accessing the data contained therein.    -   (v) The inventive concept effectively adds a new extended        indirect addressing method to all instructions capable of        accessing the linear memory management unit (LMMU).    -   (vi) The inventive concept provides simplified coding.    -   (vii) The inventive concept provides faster access to large        elements in extended memory.

In particular, it is envisaged that the aforementioned inventive conceptcan be applied by a semiconductor manufacturer to any 8/16-bitmicroprocessor architecture, for example those of the Freescale™ S08 MCUfamily. It is further envisaged that, for example, a semiconductormanufacturer may employ the inventive concept in a design of astand-alone MCU device, or application-specific integrated circuit(ASIC) and/or any other sub-system element employing an 8/16-bit MCU.

It will be appreciated that any suitable distribution of functionalitybetween different functional units or controllers or memory elements,may be used without detracting from the inventive concept hereindescribed. Hence, references to specific functional devices or elementsare only to be seen as references to suitable means for providing thedescribed functionality, rather than indicative of a strict logical orphysical structure or organization.

Aspects of the invention may be implemented in any suitable formincluding hardware, software, firmware or any combination of these. Theelements and components of an embodiment of the invention may bephysically, functionally and logically implemented in any suitable way.Indeed, the functionality may be implemented in a single unit or IC, ina plurality of units or ICs or as part of other functional units.

Although the present invention has been described in connection withsome embodiments, it is not intended to be limited to the specific formset forth herein. Rather, the scope of the present invention is limitedonly by the accompanying claims. Additionally, although a feature mayappear to be described in connection with particular embodiments, oneskilled in the art would recognize that various features of thedescribed embodiments may be combined in accordance with the invention.In the claims, the term ‘comprising’ does not exclude the presence ofother elements or steps.

Furthermore, although individual features may be included in differentclaims, these may possibly be advantageously combined, and the inclusionin different claims does not imply that a combination of features is notfeasible and/or advantageous. Also, the inclusion of a feature in onecategory of claims does not imply a limitation to this category, butrather indicates that the feature is equally applicable to other claimcategories, as appropriate.

Furthermore, the order of features in the claims does not imply anyspecific order in which the features must be performed and in particularthe order of individual steps in a method claim does not imply that thesteps must be performed in this order. Rather, the steps may beperformed in any suitable order. In addition, singular references do notexclude a plurality. Thus, references to “a”, “an”, “first”, “second”etc. do not preclude a plurality.

Thus, an improved memory management unit (MMU), and method of operationtherefor have been described, wherein the aforementioned disadvantageswith prior art arrangements have been substantially alleviated.

1. A memory management unit comprises: register and control logic andarranged to support a microprocessor controller unit accessing physicaladdress space via an address bus wherein the microprocessor controllerunit comprises a program counter having a first address size, whereinthe register and control logic comprises a register having a secondaddress size greater than the first address size and arranged to providean extended address bus between the microprocessor controller unit andphysical address space, wherein the memory management unit ischaracterised in that the register and control logic further comprisesone or more of the group consisting of: at least one register incrementfunction; a register address movement function; a register addressmaintain function.
 2. The memory management unit of claim 1 wherein theregister and control logic is operably coupled to an arithmetic logicunit arranged to point to an address in the register in response to acontrol signal.
 3. The memory management unit of claim 2 wherein thearithmetic logic unit is an adder or subtractor.
 4. The memorymanagement unit of claim 1 wherein the memory management unit isarranged to perform index-manipulation of the register in the registerand control logic.
 5. The memory management unit of claim 1 wherein theat least one register increment function increments a pointer directedto the register.
 6. The memory management unit of claim 5 furtherwherein the at least one register increment function operates as anautomatic incrementing pointer.
 7. The memory management unit of claim 1wherein the register address movement function adds a value to a pointerdirected to the register.
 8. The memory management unit of claim 1wherein the register address maintain function places a previous valuein the register on the address bus, without incrementing the register.9. The memory management unit of claim 1 wherein the register andcontrol logic is operably coupled to an output multiplexer configured toprovide a multiplexed output of an address provided by themicroprocessor controller unit and a value generated by the register andcontrol logic on an extended address bus.
 10. The memory management unitof any preceding claim 1 further characterised in that wherein theregister and control logic comprises at least one memory mapped indirectregister.
 11. The memory management unit of claim 1 wherein the registerand control logic comprises a register divided into multiple elements.12. The memory management unit of claim 1 wherein instructions handledby the microprocessor controller unit that are able to access theregister are capable of using extended addressing.
 13. An integratedcircuit comprising the memory management unit according to claim
 1. 14.A method of accessing an address in physical address space using amemory management unit comprising register and control logic, the methodcomprising: accessing physical address space, by a microprocessorcontroller unit comprising a program counter having a first addresssize, via an address bus wherein the method is comprising: providing, bya register of the register and control logic an extended address busbetween the microprocessor controller unit and physical address space asa second address size of the register is greater than the first addresssize of the program counter using one or more of the group consistingof: at least one register increment function; a register addressmovement function; a register address maintain function. 15-25.(canceled)
 26. The memory management unit of claim 2 wherein the memorymanagement unit is arranged to perform index-manipulation of theregister in the register and control logic.
 27. The memory managementunit of claim 3 wherein the memory management unit is arranged toperform index-manipulation of the register in the register and controllogic.
 28. The memory management unit of claim 2 wherein the registerand control logic is operably coupled to an output multiplexerconfigured to provide a multiplexed output of an address provided by themicroprocessor controller unit and a value generated by the register andcontrol logic on an extended address bus.
 29. The memory management unitof claim 3 wherein the register and control logic is operably coupled toan output multiplexer configured to provide a multiplexed output of anaddress provided by the microprocessor controller unit and a valuegenerated by the register and control logic on an extended address bus.30. The memory management unit of claim 4 wherein the register andcontrol logic is operably coupled to an output multiplexer configured toprovide a multiplexed output of an address provided by themicroprocessor controller unit and a value generated by the register andcontrol logic on an extended address bus.
 31. The memory management unitof claim 5 wherein the register and control logic is operably coupled toan output multiplexer configured to provide a multiplexed output of anaddress provided by the microprocessor controller unit and a valuegenerated by the register and control logic on an extended address bus.